WiNode 5 is the successor to earlier WiNodes that were based on the 28 pin DIL ATmega328.
The ATmega1284 offers significantly more features and GPIO pins, 32 compared to the 20 of the ATmega328 - and these all have to be mapped out in a way that makes sense on the PCB. There is also a constraint of 28 header pins - so four of the GPIO appear elsewhere on the pcb - for specific functions - see later.
There is no common standard, with several commercial ATmega1284 boards doing their own thing - generally based on the 40 pin DIL version of the ATmega1284.
Reverting to good ol' ASCII Art - Here is one mapping scheme from "Mighty1284P"
// +---\/---+
// (D 0) PB0 1| |40 PA0 (AI 0 / D24)
// (D 1) PB1 2| |39 PA1 (AI 1 / D25)
// INT2 (D 2) PB2 3| |38 PA2 (AI 2 / D26)
// PWM (D 3) PB3 4| |37 PA3 (AI 3 / D27)
// PWM/SS (D 4) PB4 5| |36 PA4 (AI 4 / D28)
// MOSI (D 5) PB5 6| |35 PA5 (AI 5 / D29)
// PWM/MISO (D 6) PB6 7| |34 PA6 (AI 6 / D30)
// PWM/SCK (D 7) PB7 8| |33 PA7 (AI 7 / D31)
// RST 9| |32 AREF
// VCC 10| |31 GND
// GND 11| |30 AVCC
// XTAL2 12| |29 PC7 (D 23)
// XTAL1 13| |28 PC6 (D 22)
// RX0 (D 8) PD0 14| |27 PC5 (D 21) TDI
// TX0 (D 9) PD1 15| |26 PC4 (D 20) TDO
// RX1/INT0 (D 10) PD2 16| |25 PC3 (D 19) TMS
// TX1/INT1 (D 11) PD3 17| |24 PC2 (D 18) TCK
// PWM (D 12) PD4 18| |23 PC1 (D 17) SDA
// PWM (D 13) PD5 19| |22 PC0 (D 16) SCL
// PWM (D 14) PD6 20| |21 PD7 (D 15) PWM
// +--------+
This is a fairly logical approach, with pins numbered starting from Pin 1 of the package and just following the package around. However it does not tie in well with the mapping on the Arduino or WiNode 5 board:
The Bobuino pin mapping is much more like the original Arduino - preserving D0 to D13 in their old familiar positions and functions, plus the analogue inputs mapped to D14 to D21, and the additional (Port C) pins following on as D22 to D29. This just puts SCL and SDA a little bit off beat as D22 and D23. The mapping scheme is better but not perfect:
//
// +---\/---+
// (D 4) PB0 1 | | 40 PA0 (D 21) AI 7
// (D 5) PB1 2 | | 39 PA1 (D 20) AI 6
// INT2 (D 6) PB2 3 | | 38 PA2 (D 19) AI 5
// PWM (D 7) PB3 4 | | 37 PA3 (D 18) AI 4
// PWM/SS (D 10) PB4 5 | | 36 PA4 (D 17) AI 3
// MOSI (D 11) PB5 6 | | 35 PA5 (D 16) AI 2
// PWM/MISO (D 12) PB6 7 | | 34 PA6 (D 15) AI 1
// PWM/SCK (D 13) PB7 8 | | 33 PA7 (D 14) AI 0
// RST 9 | | 32 AREF
// VCC 10 | | 31 GND
// GND 11 | | 30 AVCC
// XTAL2 12 | | 29 PC7 (D 29)
// XTAL1 13 | | 28 PC6 (D 28)
// RX0 (D 0) PD0 14 | | 27 PC5 (D 27) TDI
// TX0 (D 1) PD1 15 | | 26 PC4 (D 26) TDO
// INT0 RX1 (D 2) PD2 16 | | 25 PC3 (D 25) TMS
// INT1 TX1 (D 3) PD3 17 | | 24 PC2 (D 24) TCK
// PWM (D 30) PD4 18 | | 23 PC1 (D 23) SDA
// PWM (D 8) PD5 19 | | 22 PC0 (D 22) SCL
// PWM (D 9) PD6 20 | | 21 PD7 (D 31) PWM
// +--------+
My problem is that pins B0 and B1 are not routed to the regular headers but appear on the upper H-bridge connector JP4 and the "X-Bee" shield. Additionally Analogue inputs A6 and A7 are used on board for battery volts and battery temperature monitoring. These rogue pins need to be accounted for in the mapping scheme.This therefore gives rise to the modified arrangement:
//
// +---\/---+
// (D 30) PB0 1 | | 40 PA0 (D 22) AI 0
// (D 31) PB1 2 | | 39 PA1 (D 23) AI 1
// INT2 (D 8) PB2 3 | | 38 PA2 (D 14) AI 2
// PWM0A (D 9) PB3 4 | | 37 PA3 (D 25) AI 3
// PWM0B/SS (D 10) PB4 5 | | 36 PA4 (D 26) AI 4
// MOSI (D 11) PB5 6 | | 35 PA5 (D 27) AI 5
// PWM3A/MISO (D 12) PB6 7 | | 34 PA6 (D 28) AI 6
// PWM3B/SCK (D 13) PB7 8 | | 33 PA7 (D 29) AI 7
// RST 9 | | 32 AREF
// VCC 10 | | 31 GND
// GND 11 | | 30 AVCC
// XTAL2 12 | | 29 PC7 (D 21)
// XTAL1 13 | | 28 PC6 (D 20)
// RX0 (D 0) PD0 14 | | 27 PC5 (D 19) TDI
// TX0 (D 1) PD1 15 | | 26 PC4 (D 18) TDO
// INT0 RX1 (D 2) PD2 16 | | 25 PC3 (D 17) TMS
// INT1 TX1 (D 3) PD3 17 | | 24 PC2 (D 16) TCK
// PWM1B (D 4) PD4 18 | | 23 PC1 (D 14) SDA
// PWM1A (D 5) PD5 19 | | 22 PC0 (D 15) SCL
// PWM2B (D 6) PD6 20 | | 21 PD7 (D 7) PWM2A
// +--------+
With any pin-mapping , it is clearly a compromise between physical and logical arrangement. These changes can be incorporated into the pins_arduino.h header file. We achieve a mapping that is reasonably familiar with existing Arduino pin-out and ties in well with the physical layout of the pcb:
// _________________________________
// RXD0 (D0) |o A7 (D29) o|A5 (D27)
// TXD0 (D1) |o A6 (D28) o|A5 (D26)
// RXD1 INT0 (D2) |o B0 (D30) o|A3 (D25)
// TXD1 INT1 (D3) |o B1 (D31) o|A2 (D24)
// PWM1B (D4) |o o|A1 (D23)
// PWM1A (D5) |o o|A0 (D22)
// PWM2B (D6) |o |
// PWM2A (D7) |o |
// | o|VIN
// INT2 (D8) |o o|0V
// PWM0A (D9) |o o|0V
// PWM0B/SS (D10) |o o|+3V3
// MOSI (D11) |o o|+5V
// PWM3A MISO (D12) |o o|RES
// PWM3B SCK (D13) |o o|C5 (D21)
// 0V |o o|C4 (D20)
// AREF |o Open Hardware o|C3 (D19)
// SDA (D14) |o WiNode 5 o|C2 (D18)
// SCL (D15) |o o|C1 (D17)
// ANT |O o|C0 (D16)
// |_________________________________|
This makes for a neat, logical arrangement, where the pairs of complimentary PWM outputs are located next to one another - and in a neat group D4-D7.
SCL and SDA are on the end of the upper digitals - where you would expect them on an R3 shield.
The JTAG lines (TCK,TMS, TDI,TD0) are in a neat group on the extended headers C0-C5. C4 and C5 may be used for active signalling to the shield through the Arduino I/O and NC pins on the end of the power header.
ANT is the antenna connection to the RFM69 wireless transceiver module.
In part 3 we further name and map these pins to suit the EVITA graphics shield and the Open Inverter H-bridge module.
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