OSHUG are now in their 6th year, and meet up monthly in Central London, for discussion and socialising. I have known them since meeting #5 - but it was interest that I found this video of Professor David May, speaking at the very first OSHUG meeting #1 back in 2010 (44 minutes).
David May worked on the transputer project back in the mid 1980s, and more recently became the founder of XMOS - a fabless semicoductor company based in Bristol. XMOS make a multicore processor - that has specific hardware to support multi thread, concurrent processing.
The XMOS architecture is formally described in this pdf, or as a shortform in this slide presentation - by Professor David May.
Before I dive fully into the XMOS, I would like to suggest that we are living at a time of great innovation in terms of processor architectures, and whilst sometimes it appears that the world is powered increasingly by ARMs, there is certainly a renaissance for new ideas in computing architectures.
A few weeks ago I looked briefly at the Parallax Propeller, again a novel machine, and as I bring myself up to speed with the XMOS, I can see distinct similarities between the devices. The dev boards for these devices are low cost and widely available - so why not try something a bit different?
Both Parallax and XMOS are fairly small companies, and this might be part of the reason why they have taken innovative approaches, that might often be overlooked by the larger semiconductor manufacturers, or seen to be so far off the beaten track, that might be perceived as too much of a financial risk to the larger vendors. When you are dragged along by the momentum of the herd, there is little opportunity to innovate!
First let's look at some similarities between the XMOS and Parallax devices. They are both advertised as multicore microcontrollers, though this terminology may be a little misleading, as the XMOS device does not have true, separate stand-alone cores inside. Instead, it has an execution unit, that has access to separate banks of registers, whilst the Propeller, has multiple execution units (cogs), which have access to shared memory resources. Unless I am mistaken (and I might be, should any one wish to put me right), they appear to be two different approaches to achieve roughly the same outcome - multicore processing with virtually no latency between tasks.
The XMOS device reminds me of the Z80 architecture that had an alternate set of registers A' F' B' C' D' E' and H' L' . Both the main registers and the alternate set were connected to the internal bus via a multiplexer, which allowed fast switching between the banks using the EXX instruction. In common use, the main registers were used for the main program, until an interrupt occurred, at which point the alternate set could be switched in to be used throughout the Interrupt Service Routine - an unrelated task. The meant that the latency involved in stacking and unstacking registers could be avoided - and a faster interrupt response time achieved.
XMOS appear to take this bank swapping concept a whole stage further, and each "core" is effectively a rapidly swap-able bank of registers - consisting of 12 general purpose registers, stack pointer, data pointer, PC etc.
The banks of registers can be selected in an instant by a multiplexer structure, and this is done in a round robin fashion. I get the image of the execution unit, parking one set of registers and picking up the next to continue with a new task, rather like a turret machine tool automatically changes it's cutting bits.
The Parallax Propeller device, on the other hand, has multiple execution units with their own local set of extended registers, which have round-robin access to shared memory resources.
The difference between the two architectures may initially appear subtle, but I suspect they have their distinctive pros + cons, and part of the process of exploring new architectures is to investigate these differences - seeking out advantages in them both.
A later post will look at the all important interconnect between Xcores (xCONNECT) plus some applications.
However, as this is a bank-holiday weekend in the UK and Memorial Day in the US, I shall park this entry for the moment, allowing the interested to find time for their own reading.
Might I suggest this excellent tutorial - which introduces the architecture and looks at some coding examples.
Finally, a brief reminder - The Silicon Valley Forth Interest Group meet on Saturday 28th May. This month it is a workshop in creating an 8080 core on a Lattice FPGA and running eForth on it. Details here.