|The Papilio Duo - A Spartan 6 FPGA board with 2MB SRAM|
Today, for the first time, I have a working softcore processor running in a FPGA on the Gadget Factory Papilio Duo board.
It's a J1b Forth cpu which is a 32 bit, minimum instruction set stack processor.
Thanks to James Bowman, the J1 designer at Excamera Labs for supplying the bitfile, of a slightly speed reduced variant that now programs and runs on my newest Papilio Duo Spartan 6 FPGA board.
James has supplied his "SwapForth" that is an ANS 94 compatible Forth - with some extensions to suit the Papilio hardware, embedded into the bitfile, used to program the FPGA.
I was still having some beginners teething troubles with Python, for the communications shell, so I am running the serial comms using Termite - a Terminal application. It is important to ensure that DTR is set low - otherwise the board is held in reset. Once I sorted that out - the J1b sprang into life.
Forth was devised in the 1960's by Charles H. Moore, and then commercially exploited in the 1970s. It is a very compact language and is well suited to microprocessors that have limited memory resources. Moore went on in the 80's and 90's to design specialist VLSI processor ICs that were optimised to run the Forth language - at blistering speed. James Bowman's J1b is a FPGA open-core - which continues along this tradition of high speed Forth - oriented hardware.
Forth is an interesting language - with an unusual Reverse Polish syntax - that slowly grows on you, the more you use it.
Forth is also a fast executing language - especially on a processor that has been optimised in the design to execute Forth almost as its native machine language.
This build (80MHz) of the J1b can execute 10 million empty DO LOOPs per second - so to confirm the timing I tried a billion empty DO LOOPs - and the execution time is almost exactly 100 seconds. So the cycle time for a DO LOOP is 100nS.
I then placed an ADD instruction in the empty do loop and proved that it can sum a sequence of 100,000,000 integers in about 23 seconds.
This version of the J1b is clocked at 80MHz, so the instruction cycle time is 12.5nS - so it looks like the DO LOOP structure is using 8 instructions to get around the loop. If the full Forth DO LOOP structure is not needed - but just a repeated call to a block of code N times - then it might be possible to optimise this construct for speed. My initial experiments in the J1 simulator in machine language suggest that it might be possible to get around a loop in fewer cycles
When it comes to toggling an I/O pin under processor control - the J1b can do about 8MHz using it's io! word to toggle the pin. This makes direct writing of video to a VGA port a possibility.
The J1 is a soft core processor waiting to be discovered. James's SwapForth makes it relatively easy to program.
Additions to the Design
The implementation of the J1b on the Spartan 6LX9 uses only about 25% of the available logic blocks.
This leaves plenty room for implementing other hardware - including specialist video and audio generation modules - something that the people at Gadget Factory are good with.
James developed the "Gameduino" a few years ago, which used the J1 as a graphics co-processor to generate arcade game style graphics, and audio. There is an opportunity to use the remaining logic blocks to create a similar application.
The Papilio Duo makes use of "shields" to allow additional hardware to be connected. One of these is the Computing Shield, which provides break-out to the following common interfaces.
15 Pin VGA connector for RGB 4:4:4 VGA Video
9 Pin RS232 Serial COM Port
Dual Atari joystick/game controllers
Dual audio 3.5mm jacks
4 User LEDs
4 User Buttons
Grove expansion connector.
The combination of the J1b, plus a second J1 running the graphics, and the low cost hardware from Gadget Factory could make for a very interesting computing platform.